1. Field of the Invention
The present invention relates to a memory device having multiple ports, and more particularly to a memory device capable of reducing a cross coupling noise between the signals of the multiple ports.
2. Description of the Related Art
For a memory device having multiple ports, there has conventionally been proposed a register file to be used in a CPU. In general, the register file comprises a write port and a read port. In particular, a register file having a plurality of read ports and a plurality of write ports is often used in order to cope with many uses.
FIG. 27 is a circuit diagram showing an example of the structure of a memory cell of a conventional register file having two write ports and three read ports. In FIG. 27, a memory cell is constituted by transfer gates 1 and 2 for inputting write data, a storage element including inverters 3 and 4 for storing data, and NMOS transistors 5 to 10 for reading data from the storage element.
For signal lines to control the write and read of the memory cell, furthermore, there are provided write word lines 11 and 12 for the two ports, write bit lines 13 and 14 for the respective ports, read word lines 15 to 17 for the three ports, and read bit lines 18 to 20 for the respective ports.
FIG. 28 is a block diagram showing an example of the structure of a register file including the memory cells, each having the structure as shown in FIG. 27. In FIG. 28, the register file comprises a memory cell array 200 having the memory cells arranged with a 32-entry and 32-bit structure, an address decoder 210 for generating the address of the memory cell, a read data holding circuit 220 for holding data read from the memory cell, a write data holding circuit 230 for holding data to be written to the memory cell, and a control circuit 240.
A 4-bit address for each of the two write ports and a 5-bit address for each of the three read ports are given from the outside to the register file. The address decoder 210 decodes the given addresses and is connected to the memory cell array 200 with 64 write word lines having 32 entries and 2 ports and 96 read word lines having 32 entries and 3 ports. The read data holding circuit 220 and the memory cell array 200 are connected to each other with 3-port read bit lines, each of which has 32 bits, and the write data holding circuit 230 and the memory cell array 200 are connected to each other with 2-port write bit lines, each of which has 32 bits.
FIG. 29 is a timing chart for explaining the operation of the register file illustrated in FIGS. 26 and 27. The register file is operated synchronously with a clock signal CLK, and carries out reading at the H level of the clock signal CLK and writing at the L level thereof.
In FIG. 29, when the clock signal CLK has the L level, a write word line specified by the write address of a selected port is set to have the H level. With a port number of 0 and a word number of 1, the transfer gate 1 is turned ON in FIG. 27. Consequently, the data of the write bit line 13 having the port number of 0 are stored in the storage element having the word number of 1 through the transfer gate 1.
When the clock signal CLK has the H level, a read word line specified by the read address of a selected port is set to have the H level. With the port number of 0 and the word number of 1, the transistor 5 is turned ON in FIG. 27. Consequently, data stored in the storage element having the word number of 1 are read onto the read bit line 18 having the port number of 0 through the transistor 6.
A semiconductor integrated circuit has continually progressed a semiconductor technology to meet a requirement for an increase in integration without an end and microfabrication has further made progress in a semiconductor processing. With the microfabrication of the semiconductor processing, a malfunction caused by a cross coupling noise between adjacent bit lines or word lines has further been serious.
With the microfabrication, moreover, it is necessary to reduce a drain leakage when dropping a source voltage to carry out a writing operation to a memory cell. When the drain leakage is reduced, the threshold of the transistor is increased. For this reason, there is a problem in that ideal scaling corresponding to the microfabrication cannot be always carried out and it is hard to drop the source voltage.
In order to carry out a microfabrication processing, moreover, an exposure wavelength is reduced in a manufacturing process. In order to realize the function and characteristic of the memory cell, it is desirable that the mask data of a transistor should be optimized according to a reduction in a wavelength or an optical phase correction should be individually carried out in exposure. However, an enormous man-hour is required for the optimization of the mask data, and furthermore, it is hard to carry out a partial optical phase correction because the exposure is performed for a whole wafer. Accordingly, there is a problem in that the memory cell is to be designed on the assumption that the mask data which can be compromised to some extent are used.